Present day integrated circuits (IC) are designed using a variety of software tools, known in the art as Design Automation tools. These tools encompass data entry capture, simulation, partitioning of logic, synthesis, wiring and placement, testing, etc. One of the tools which are deemed essential to the design of any IC product, whether a chip, module, card, board, frame, and the like, is known as a ground rules checker. Ground rules checking is the process of verifying that a mask layout of an integrated circuit does not violate a set of predefined geometrical design rules, also referred to as ground rules. These rules are, typically, determined by the manufacturing process (also known as the plan of record) used to fabricate the integrated circuit. Ground rules are thus a collection of geometrical constraints among geometrical shapes that define the layout of an IC. It is presumed that a circuit design which obeys the ground rules for a particular process should be manufacturable when using that process. Accordingly, ground rules checking is an essential step in any IC design process.
IC designs are generally expressed as a geometrical description of the layout organized hierarchically in a data file. Consequently, an error within the hierarchy may give rise to many violations of the ground rules throughout the design, and which because of the hierarchy, oftentimes, represent the same error replicated many times. If this is realized, particularly, during early stages of the design phase, it may be possible for the designer to intervene only once in the hierarchy in order to rectify the error.
Known ground rules checkers can be divided into two classes according to the algorithmic approach and internal architecture: (i) Flat ground rules checkers which treat each polygon on a flattened layout as an independent entity, and (ii) Hierarchical checkers, which exploit the hierarchy to direct the traversal of the data.
An example of a flat ground rules checker can be found in IEEE Design and Test of Computers, Vol 2, No. 3, pp. 64-72 (1985).
Examples of hierarchical ground rules checkers can be found in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol CAD-6, No. 4, pp. 561-573 (1987), Vol 9, No. 1, pp. 66-90 (1990) and Vol 12, No. 2 pp. 265-272 (1993).
Flat ground rules checkers report all the instances of an error without regard of the source of the error. Its main disadvantage resides in that the report contains much redundant and irrelevant information and that the amount of work required to rectify the error is not apparent from the report. Hierarchical checkers, on the other hand, are complicated to implement and less efficient for structures which are not highly nested or well structured.